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Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD10465
utilize an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. The AD10465 uses innovative highdensity circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance, while still maintaining excellent isolation and providing for significant board area savings. The AD10465 operates with 5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent encode and analog inputs. The AD10465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. The AD10465 is packaged in a 68-lead Ceramic Gull Wing package, footprint-compatible with the earlier generation AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufacturing is done on Analog Devices, Inc. Mil-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (-40C to +85C). The AD6644 internal components are manufactured on Analog Devices, Inc. high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-to-Channel Matching, 0.5% Gain Error Channel-to-Channel Isolation, >90 dB DC-Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range ( 0.5 V, 1.0 V, 2.0 V) Gain Flatness up to 25 MHz: < 0.2 dB 80 dB Spurious-Free Dynamic Range Two's Complement Output Format 3.3 V or 5 V CMOS-Compatible Output Levels 1.75 W per Channel Industrial and Military Grade APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Antijamming Receivers Multichannel, Multimode Receivers PRODUCT DESCRIPTION
The AD10465 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6644 ADCs. Each AD6644 has a dccoupled amplifier front end including an AD8037 low distortion, high bandwidth amplifier, providing a high input impedance and gain, and driving the AD8138 single-to-differential amplifier. The AD6644s have on-chip track-and-hold circuitry and
1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance. 5. Footprint compatible family; 68-lead LCC.
FUNCTIONAL BLOCK DIAGRAM
AINA3 AINA2 AINA1 REF A AINB3 AINB2 AINB1
DRAOUT D0A (LSB) D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A TIMING ENC ENC 11 VREF DROUT 14 OUTPUT BUFFERING 3 VREF DROUT 14 OUTPUT BUFFERING 9 5 REF B DRBOUT
AD10465
ENC TIMING ENC D13B D12B D11B D10B D9B
D11A D12A D13A (MSB)
D0B (LSB) D1B D2B D3B D4B D5B
D6B D7B D8B
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD10465-SPECIFICATIONS (AV
Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error1 Gain Error Channel Match
CC
= +5 V; AVEE = -5 V; DVCC = 3.3 V applies to each ADC unless otherwise noted.)
Test Level Mil Subgroup AD10465AZ/BZ/QML-H Min Typ Max 14 Unit Bits
Temp
Full 25C Full Full 25C Full 25C Max Min
VI I VI V I VI I I I
1, 2, 3 1 2, 3 1 2, 3 1 2 3
-2.2 -2.2 -1 -3 -5 -1.5 -3 -5
Guaranteed 0.02 1.0 1.0 -1.0 2.0 0.5 1.0
+2.2 +2.2 +1 +1 +5 +1.5 +3 +5
% FS % FS % % FS % FS % % %
ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth3 ENCODE INPUT (ENC, ENC)4 Differential Input Voltage 17 Differential Input Resistance Differential Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate 5 Minimum Conversion Rate 5 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay (T E_DR) SNR6 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz SINAD7 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz
Full Full Full Full Full Full 25C Full Full 25C 25C Full Full 25C 25C 25C 25C 25C Full Full 25C 25C Full 25C Full 25C Full 25C 25C Full 25C Full 25C Full
V V V IV IV IV IV V IV V V VI V V IV V IV IV V 4, 5, 6 12 12 12 12 6.2 6.2 12 12 12 12 99 198 396 0
0.5 1.0 2 100 200 400 4.0 100 101 202 404 7.0
V V V pF MHz V p-p k pF MSPS MSPS ns ps ps rms ns ns ns ns dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB dB dB dB dB dB dB
0.4 10 2.5 65 20 1.5 250 0.3 7.7 7.7 6.8 11.5 70 70 70 70 70 69 69 70 69 69 68 68 63 61 500 9.2 9.2
V I II I II I II V I II I II I II
4 5, 6 4 5, 6 4 5, 6
69 68 68 67 67 67
4 5, 6 4 5, 6 4 5, 6
67.5 67.5 65 65 60 58
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Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz TWO-TONE IMD REJECTION 9 fIN = 10 MHz and 11 MHz f1 and f2 are -7 dB fIN = 31 MHz and 32 MHz f1 and f2 Are -7 dB CHANNEL-TO-CHANNEL ISOLATION 10 TRANSIENT RESPONSE OVERVOLTAGE RECOVERY TIME VIN = 2.0 x fS VIN = 4.0 x fS DIGITAL OUTPUTS 12 Logic Compatibility DVCC = 3.3 V Logic "1" Voltage Logic "0" Voltage DVCC = 5 V Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY AVCC Supply Voltage13 I (AVCC) Current AVEE Supply Voltage13 I (AVEE) Current DVCC Supply Voltage13 I (DVCC) Current ICC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) Passband Ripple to 10 MHz Passband Ripple to 25 MHz
11 8
Temp 25C 25C Full 25C Full 25C Full 25C 25C Full 25C 25C Full Full
Test Level V I II I II I II I II I II IV V IV IV
Mil Subgroup
AD10465AZ/BZ/QML-H Min Typ Max 85 82 82 78 78 68 66 87 70 90 15.3
Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB ns
4 5, 6 4 5, 6 4 5, 6 4 5, 6 4 5, 6 12
73 70 72 70 62 60 78 78 68 60
12 12
40 150 CMOS
100 200
ns ns
Full Full Full Full
I I V V
1, 2, 3 1, 2, 3
2.5
DVCC - 0.2 0.2
0.5
V V V V
DVCC - 0.3 0.35 Two's Complement 4.85 -5.25 3.135 1, 2, 3 1, 2, 3 5.0 270 -5.0 38 3.3 30 338 3.5 0.02 0.1 0.2 5.25 308 -4.75 49 3.465 46 403 3.9
Full Full Full Full Full Full Full Full Full
VI I VI V VI V I I V V V
V mA V mA V mA mA W % FSR/% VS dB dB
NOTES 1 Gain tests are performed on A IN1 input voltage range. 2 Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 All ac specifications tested by driving ENCODE and ENCODE differentially. 5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% 5%. 6 Analog input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full power. 7 Analog input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. 8 Analog input signal power swept from -1 dBFS to -60 dBFS; SFDR is ratio of converter full scale to worst spur. 9 Both input tones at -7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 11 Input driven to 2x and 4x AIN1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS. 12 Digital output logic levels: DV CC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 13 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. All specifications guaranteed within 100 ms of initial power-up regardless of sequencing. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL2 Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Min Max Units 0 -7 VEE -10 0 -10 -40 7 0 VCC +10 VCC 4 +10 +85 174 300 +150 V V V mA V V mA C C C C TEST LEVEL
I. 100% Production Tested. II. 100% Production Tested at 25C, and sample tested at specified temperatures. AC testing done on sample basis. III. Sample Tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at temperature at 25C, sample tested at temperature extremes.
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NOTES 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for "ES" package: JC = 2.2C/W; JA = 24.3C/W.
ORDERING GUIDE
Model AD10465AZ AD10465BZ 5962-9961601HXA AD10465/PCB
Temperature Range -25C to +85C (Case) -40C to +85C (Case) -40C to +85C (Case) 25C
Package Description 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD10465AZ
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10465 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN FUNCTION DESCRIPTIONS
Pin No. 1 2, 4, 5, 9-11 3 6 7 8 12 13 14 26, 27 15-25, 31-33 28 29 30 43, 44 34-42, 45-49 53-54, 57-61, 65, 68 50 51 52 55 56 62 63 64 66 67
Name SHIELD AGNDA REF_A AINA1 AINA2 AINA3 DRAOUT AVEE AVCC DGNDA D0A-D13A ENCODEA ENCODEA DVCC DGNDB D0B-D13B AGNDB DVCC ENCODEB ENCODEB DRBOUT REF_B AINB1 AINB2 AINB3 AVCC AVEE
Function Internal Ground Shield between channels. A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. A Channel Internal Voltage Reference. Analog Input for A side ADC (nominally 0.5 V). Analog Input for A side ADC (nominally 1.0 V). Analog Input for A side ADC (nominally 2.0 V). Data Ready A Output. Analog Negative Supply Voltage (nominally -5.0 V or -5.2 V). Analog Positive Supply Voltage (nominally 5.0 V). A Channel Digital Ground. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital Positive Supply Voltage (nominally 5.0 V/3.3 V). B Channel Digital Ground. Digital Outputs for ADC B. D0 (LSB). B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally 5.0 V/3.3 V). Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Data Ready B Output. B Channel Internal Voltage Reference. Analog Input for B side ADC (nominally 0.5 V). Analog Input for B side ADC (nominally 1.0 V). Analog Input for B side ADC (nominally 2.0 V). Analog Positive Supply Voltage (nominally -5.0 V). Analog Negative Supply Voltage (nominally -5.0 V or -5.2 V). .
PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier
SHIELD AGNDB AVCC AGNDB A IN B3 AGNDA AGNDA REF A AGNDA AGNDA AVEE AGNDB
60 AGNDB 59 AGNDB 58 AGNDB 57 AGNDB 56 REF B 55 DRBOUT 54 AGNDB 53 AGNDB 52 ENCODEB 51 ENCODEB 50 DVCC 49 D13B(MSBB) 48 D12B 47 D11B 46 D10B 45 D9B 44 DGNDB 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9
8
AINA1 AINA2 AINA3
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER
AGNDA 10 AGNDA 11 DRAOUT 12 AVEE 13 AVCC 14 D0A(LSBA) 15 D1A 16 D2A 17 D3A 18 D4A 19 D5A 20 D6A 21 D7A 22 D8A 23 D9A 24 D10A 25 DGNDA 26
AD10465
TOP VIEW (Not to Scale)
D1B
D2B
D4B
D5B
D6B
D3B
D7B
D8B
A IN B2 A IN B1
ENCODEA ENCODEA
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D12A D13A(MSBA)
D0B(LSBB)
DGNDA
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DGNDB
DVCC D11A
AD10465-Typical Performance Characteristics
0 -10 -20 -30 -40 -50
dB dB
0
ENCODE = 65MSPS AIN = 5MHz (-1dBFS) SNR = 71.02 SFDR = 92.11dBc
-10 -20 -30 -40 -50 -60 -70 -80
ENCODE = 65MSPS AIN = 10MHz (-1dBFS) SNR = 70.79 SFDR = 86.06dBc
-60 -70 -80 -90 -100 -110 -120 -130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY - MHz 2 3 4 5 6
2 5 6 4
3
-90 -100 -110 -120 -130 0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY - MHz
TPC 1. Single Tone @ 5 MHz
TPC 4. Single Tone @ 10 MHz
0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 20MHz (-1dBFS) SNR = 70.71 SFDR = 79.73dBc
0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 25MHz (-1dBFS) SNR = 70.36 SFDR = 74.58dBc
dB
dB
-60 -70 -80 -90 -100 -110 -120 -130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY - MHz 6 4 3 2 5
-60 -70 -80 -90 -100 -110 -120 -130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY - MHz 5 6 4 3 2
TPC 2. Single Tone @ 20 MHz
TPC 5. Single Tone @ 25 MHz
0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 32MHz (-1dBFS) SNR = 70.22 SFDR = 66.40dBc
100 90 SFDR 80 70 60 2 -dBc 3 50 40 6 4 5 30 20 10 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY - MHz 4.989 9.989 19.000 32.000 INPUT FREQUENCY - MHz SINAD
dB
-60 -70 -80 -90 -100 -110 -120 -130
TPC 3. Single Tone @ 32 MHz
TPC 6. SFDR and SINAD vs. Frequency
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0 -10 -20 -30 -40 -50
dB dB
0 ENCODE = 65MSPS AIN = 9MHz AND 10MHz (-7dBFS) SFDR = 82.83dBc -10 -20 -30 -40 -50 -60 -70 -80 F2- F1 -90 -100 -110 -120 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY - MHz -130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY - MHz 2F2+ F1 2F1+ F2 ENCODE = 65MSPS AIN = 17MHz AND 18MHz (-7dBFS) SFDR = 77.68dBc
-60 -70 -80 F2- -90 F1 -100 -110 -120 -130 2F1- F2 2F2- F1 F1+ F2 2F1+ F2 2F2+ F1
2F1- F2
2F2- F1
F1+ F2
TPC 7. Two Tone @ 9/10 MHz
TPC 10. Two Tone @ 17/18 MHz
3.0 2.5 2.0 ENCODE = 65MSPS DNL MAX = +0.549 CODES DNL MIN = -0.549 CODES
3.0 ENCODE = 65MSPS INL MAX = +1.173 CODES INL MIN = -1.332 CODES
2.0
1.0 1.5
LSB
LSB
1.0 0.5
0
-1.0 0 -0.5 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 -2.0
-3.0 0 2048 4096 6144 8192 10240 12288 14336 16384
TPC 8. Differential Nonlinearity
TPC 11. Integral Nonlinearity
0 -1 -2 -3
72.0 71.5 -40 C 71.0 70.5
-4 -5 -6 -7 -8 -9 -10 1.0 4.2 7.4 10.6 13.8 17.0 20.2 23.4 26.6 29.8 33.0
69.0 68.5 68.0 67.5 5
+25 C
SNRFS
dBFS
70.0 +85 C 69.5
10 AIN - MHz
19
32
FREQUENCY - MHz
TPC 9. Gain Flatness
TPC 12. SNR vs. AIN Frequency
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DEFINITION OF SPECIFICATIONS Analog Bandwidth Overvoltage Recovery Time
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. May be reported in dB (i.e., relative to signal level) or in dBFS (always related back to converter full scale).
Signal-to-Noise Ratio (without Harmonics)
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic "1" state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dB (i.e., relative to signal level) or in dBFS (always related back to converter full scale).
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic.
Transient Response
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The time required for the converter to achieve 0.03% accuracy when a one-half full-scale step function is applied to the analog input.
Two-Tone Intermodulation Distortion Rejection
The encode rate at which parametric testing is performed, above which converter performance may degrade.
Output Propagation Delay
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBFS.
The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.
tA
N AIN N+1 N+2 N+4 N+3
t ENC
ENC, ENC N
t ENCH
N+1
t ENCL
N+2 N+3
N+4
t E, DR
D[13:0] N-3 N-2 N-1 N
t OD
DRY
Figure 1. Timing Diagram
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AVIN3 200 AVIN2 100 AVIN1 100 TO AD8037
DVCC CURRENT MIRROR
DVCC VREF
Figure 2. Analog Input Stage
LOADS AVCC AVCC 10k ENCODE 10k 10k 10k ENCODE AVCC AVCC
DR OUT
CURRENT MIRROR
Figure 4. Digital Output Stage
DVCC
LOADS
CURRENT MIRROR
Figure 3. ENCODE Inputs
THEORY OF OPERATION
DVCC VREF 100 D0-D13
The AD10465 is a high dynamic range 14-bit, 65 MHz pipeline delay (three pipelines) analog-to-digital converter. The custom analog input section maintains the same input ranges (1 V p-p, 2 V p-p, and 4 V p-p) and input impedance (100 , 200 , and 400 ) as the AD10242. The AD10465 employs four monolithic ADI components per channel (AD8037, AD8138, AD8031, and AD6644), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14-bit analog-to-digital converter. The input signal is passed through a precision laser-trimmed resistor divider allowing the user to externally select operation with a full-scale signal of 0.5 V, 1.0 V or 2.0 V by choosing the proper input terminal for the application. The AD10465 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers inputs and outputs. The AD8037 amplifier provides a high input impedance and gain for driving the AD8138 in a single-ended to differential amplifier configuration. The AD8138 has a -3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the AD6644, maximizing the performance of the ADC. The AD8031 provides the buffer for the internal reference of the AD6644. The internal reference voltage of the AD6644 is designed to track the offsets and drifts of the ADC and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common mode input on the AD8138. The AD6644 reference voltage sets the output common-mode on the AD8138 at 2.4 V, which is the midsupply level for the AD6644. The AD6644 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing 0.55 V around this reference. Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peak-to-peak. Both analog inputs are buffered prior to the first track-and-hold,
CURRENT MIRROR
Figure 5. Digital Output Stage
TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives 14 bits of precision which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as two's complement.
USING THE FLEXIBLE INPUT
The AD10465 has been designed with the user's ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. While the standard inputs are 0.5 V, 1.0 V and 2.0 V, the user can select the input impedance of the
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AD10465 on any input by using the other inputs as alternate locations for GND or an external resistor. The following chart summarizes the impedance options available at each input location: AIN1 = AIN1 = AIN1 = AIN2 = AIN2 = AIN2 = AIN2 = AIN3 = AIN3 = AIN3 = AIN3 = 100 when AIN2 and AIN3 are open. 75 when AIN3 is shorted to GND. 50 when AIN2 is shorted to GND. 200 when AIN3 is open. 100 when AIN3 is shorted to GND. 75 when AIN2 to AIN3 has an external resistor of 300 , with AIN3 shorted to GND. 50 when AIN2 to AIN3 has an external resistor of 100 , with AIN3 shorted to GND. 400 . 100 when AIN3 has an external resistor of 133 to GND. 75 when AIN3 has an external resistor of 92 to GND. 50 when AIN3 has an external resistor of 57 to GND.
VT 0.1 F ENCODE ECL/ PECL 0.1 F
AD10465
ENCODE
VT
Figure 7. Differential ECL for Encode
Jitter Considerations
The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter.
APPLYING THE AD10465 Encoding the AD10465
1 + N + 2 2 SNR = -20 x log (2 x x f ANALOG x t J rms) 2 VNOISE RMS 2N
fANALOG tJ RMS N = analog input frequency.
+
1/2
(1)
The AD10465 encode signal must be a high quality, extremely low phase noise source, to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 32 MHz input signals when using a high-jitter clock source. See Analog Devices' Application Note AN-501, "Aperture Uncertainty and ADC System Performance" for complete details. For optimum performance, the AD10465 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Shown below is one preferred method for clocking the AD10465. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD10465 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD10465, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 ) is placed in the series with the primary.
CLOCK SOURCE 0.1nF 100 T1-4T
= rms jitter of the encode (rms sum of encode source and internal encode circuitry). = average DNL of the ADC (typically 0.50 LSB). = Number of bits in the ADC.
VNOISE RMS = V rms noise referred to the analog input of the ADC (typically 5 LSB). For a 14-bit analog-to-digital converter like the AD10465, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD10465 as jitter increases. The chart is derived from the above equation. For a complete discussion of aperture jitter, please consult Analog Devices' Application Note AN-501, "Aperture Uncertainty and ADC System Performance."
71 70 69 68 SNR - dBFS 67 66 65 64 63 62 AIN = 32MHz 61 60 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 0.1 0.3 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 3.9 RMS CLOCK JITTER - ps AIN = 20MHz AIN = 10MHz AIN = 5MHz
ENCODE
AD10465
ENCODE HSMS2812 DIODES
Figure 6. Crystal Clock Oscillator, Differential Encode
If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola.
Figure 8. SNR vs. Jitter
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AD10465
Power Supplies LAYOUT INFORMATION
Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be "received" by the AD10465. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD10465 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD10465 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs.
Output Loading
The schematic of the evaluation board (Figure 10) represents a typical implementation of the AD10465. The pinout of the AD10465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate.
EVALUATION BOARD
Care must be taken when designing the data receivers for the AD10465. The digital outputs drive an internal series resistor (e.g., 100 ) followed by a gate like 75LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 10. The digital outputs of the AD10465 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF x 1 V, / 1 ns) of dynamic current per bit will flow in or out of the device. A full-scale transition can cause up to 140 mA (14 bits x 10 mA/bit) of current flow through the output stages. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD10465. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads.
The AD10465 evaluation board (Figure 9) is designed to provide optimal performance for evaluation of the AD10465 analogto-digital converter. The board encompasses everything needed to insure the highest level of performance for evaluating the AD10465. The board requires an analog input signal, encode clock and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD10465. The digital outputs of the AD10465 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required.
Figure 9a. Evaluation Board Mechanical Layout
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AD10465
J1 AINB3 AGNDB J2 AINB2 AGNDB J22 AINB1 AGNDB J7 AINA3 AGNDA J8 AINA2 AGNDA C59 10 F AGNDB -5.2VAB 47 AT 100MHz L9 47 47 AT 100MHz L8 47 +5VAB CLKLATCHA2 CLKLATCHB1 JP3 DRBOUT DRAOUT JP4 CLKLATCHA1 74LCX00M JP6 LATCHA 74LCX00M 74LCX00M JP2 BUFLATA 1 2 1 2 74LCX00M JP5 CLKLATCHB2 LATCHB JP1 6 BUFLATB
U2:A
3
13 12
U2:D
11
4 5
U2:B
74LCX00M
74LCX00M
U4:A
3
13 12
U4:D
11
4 5
U4:B
6
C52 10 F AGNDB
AGNDA
J20 AINA1 C57 0.1 F AGNDA
+5VAB 67 66 65
AINA3 AINA2 AINA1
9 8 7 6 5 4 3 2 1 68
64 63 62
+5VAB AGNDB AINB3 AINB2
-5.2VAA L10 C22 10 F AGNDA +5VAA L7 C53 10 F AGNDA 47 47 AT 100MHz 47
DRAOUT +5VAA D0A D1A D2A D3A D4A D5A D6A D7A D8B D9A D10A
DGNDA ENCAB ENCA +3.3VDA D11A D12A D13A(MSB)
DGNDA
D0B(LSB) D1B D2B 37 D3B 38 D4B 39 D5B 40 D6B 41 D7B 42 D8B 43 DGNDB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SHIELD AGNDB -5.2VAB
AINB1 AGNDB
AGNDA AINA3
AINA2 AINA1 AGNDA AGNDA REFA AGNDA
AGNDA AGNDA AGNDA DRAOUT -5.2VAA +5VAA D0A(LSB) D1A D2A D3A D4A D5A D6A D7A D8B D9A D10A
61
AINB3 AINB2 AINB1
U1
AD10465
AGNDB AGNDB AGNDB AGNDB REFB DRBOUT AGNDB AGNDB ENCBB ENCB +3.3VDB D13B(MSB) D12B D11B D10B D9B DGNDB
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 AGNDB
C61 0.1 F DRBOUT AGNDB ENCBB ENCB DUT 3.3VDB D13B(MSB) C64 0.1 F D12B D11B D10B D9B
L6 47
+3.3VDB
C58 10 F
DGNDB
ENCAB ENCA
DUT 3.3VDA D11A D12A D13A DB0B
D1B D2B D3B
27 28 29 30 31 32 33 34 35 36
D4B D5B D6B D7B
DGNDA
D8B
DGNDB
L11 +3.3VDA C62 10 F DGNDA 47
DUT 3.3VDB C63 0.1 F DGNDA C26 0.1 F 9
SPARE GATE 10
DUT 3.3VDA
SPARE GATE 10 9
U2:C
8
C27 0.1 F
U4:C
8
74LCX00M DGNDB DGNDB DGNDA
74LCX00M
DGNDA
Figure 9b. Evaluation Board
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AD10465
+5VAA U6 2
ADP3330
IN OUT NR SD ERR GND 4
1 8 3 C45 100pF AGNDA
6 +5VAA
J6 ENCODEA AGNDA
C42 0.1 F
JP11 OPEN R140 33k
AGNDA U7 C44 0.1 F VCC Q Q VEE 8 7 6 5 C41 0.47 F R89 100 C49 0.1 F ENCA R94 100 ENCAB
R82 51
AGNDA J18 ENCODEA AGNDA R83 51 JP8 JP7 C40 0.1 F
1 2 3 4
NC D D VBB
AGNDA
MC10EP16D NC = NO CONNECT AGNDA
AGNDA
AGNDA
+5VAA
U8 2
ADP3330
IN OUT NR SD ERR GND 4
1 8 3 C43 100pF AGNDB
6 +5VAA
J16 ENCODEB AGNDB
C37 0.1 F
JP12 OPEN R141 33k
AGNDB U9 C48 0.1 F VCC Q Q VEE 8 7 6 5 C38 0.47 F R95 100 C46 0.1 F ENCBB R97 100 ENCB
R76 51
AGNDB J17 ENCODEB AGNDB R79 51 JP10 JP9 C39 0.1 F
1 2 3 4
NC D D VBB
AGNDB
MC10EP16D NC = NO CONNECT AGNDB
AGNDB
AGNDAB
Figure 9c. Evaluation Board
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AD10465
OUT 3.3VDA U21 C13 0.1 F C14 0.1 F C15 0.1 F C20 0.1 F LATCHA DGNDA BANANA JACKS FOR GNDS AND PWRS (LSB) D0A +5VAB +5VAA E1 DGNDA E2 E3 E4 E5 E6 E7 E8 E10 E9 D6A D7A D8A D9A D10A D11A D12A (MSB) D13A +3.3VDB R100 0 R99 0 D1A D2A D3A D4A D5A VCC R98 51 25 24 VCC CP2 VCC 42 31 7 16 R114 100 R113 100 R105 100 R104 100 R106 100 R118 51 BUFLATA R103 100 R102 100 R101 100 R109 100 R108 100 R107 100 R110 100 R111 100 DGNDA MSB 20 19 18 17 16 15 14 13 12 11 10 9 8 20 19 18 17 16 15 14 13 12 11 10 9 8 21 22 23 24 25 26 27 28 29 30 31 32 33 21 22 23 24 25 26 27 28 29 30 31 32 33 R115 100 R116 100 OUT 3.3VDA R117 100
+3.3VDA
OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND
VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8
O7 O6 O5 O4 O3 O2 O1 O0 GND GND
12 11 9 8 6 5 3 2 21 15
18 GND 4 GND
7 7 6 6 5 5 4 4 3 3 2 2 1 1 J3
34 34 35 35 36 36 37 37 38 38 39 39 40 40
74LCX163743MTD -5.2VAB -5.2VAA AGNDA DGNDB
DGNDA
AGNDB
DGNDA
OUT 3.3VDA U22 C25 0.1 F C21 0.1 F C23 0.1 F C24 0.1 F LATCHB DGNDB E87 E88 E89 E139 E143 E146 E148 E149 E152 E153 E184 E188 E189 E190 E195 E197 E199 E201 E203 E205 E224 E226 E159 E160 E161 E167 E168 E169 E170 E178 E180 E182 E183 E191 E192 E193 E208 E210 E212 E214 E216 E218 E220 E222 E228 E230 E232 E234 DGNDB VCC R119 51 25 24 VCC CP2 VCC
OUT 3.3VDB 42 31 7 R125 100 R127 100
R112 100
R126 100
(LSB) D0B R123 0 R124 D1B 0 D2B D3B D4B D5B DGNDB
E72 E140 E141 E142 E144 E145 E147 E150 E151 E154 E185 E194 E196 E198 E200 E202 E204 E206 E223 E225
DGNDA
AGNDA
E162 E163 E164 E165 E166 E171 E172 E177 E179 E181 E186 E187 E207 E209 E211 E213 E215 E217 E219 E221 E227 E229 E231 E233
D6B D7B D8B D9B D10B D11B D12B (MSB) D13B
OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND
16 VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8
R130 100 R129 100 R128 100 R134 100 R137 51 BUFLATB R135 100 R136 100 R131 100 R132 100 R133 100 R120 100 R121 100 R122 100 MSB
20
20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 44 33 2 1 2 1 J4
21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 31 32 30 31 32
O7 O6 O5 O4 O3 O2 O1 O0 GND GND
12 11 9 8 6 5 3 2 21 15
18 GND 4 GND
33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40
74LCX163743MTD
DGNDB
AGNDB
DGNDB
Figure 9d. Evaluation Board
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AD10465
Bill of Materials List for AD10465 Evaluation Board
Reference Qty Designator 2 2 U2, U4 U21, U22 Value Description IC, Low-Voltage Quad 2-Input Nand, SOIC-14 IC, 16-Bit Transparent Latch with Three-State Outputs, TSSOP-48 DUT, IC 14-Bit Analog-to-Digital Converter IC, Voltage Regulator 3.3 V, RT-6 Manufacturer and Part Number Toshiba/TC74LCX00FN Fairchild/74LCX163743MTD Component Name 74LCX00M 74LCX163743MTD
1 2
U1 U6, U8
ADI/AD10465AZ Analog Devices/ADP3330ART-3, 3-RLT Johnson Components/08-0740-001 Mena/GRM40X7R104K025BL
ADI/AD10465AZ ADP3330
10 22
E1-E10 C13-C15, C20, C21, C23-C27, C37, C39, C40, C42, C44, C46, C48, C49, C57, C61, C63, C64 C38, C41 C43, C45 J3, J4 L6-L11 U7, U9 C22, C50, C52, C53, C59, C62 R99, R100, R123, R124 R140, R141 R76, R79, R82, R83, R98, R118, R119, R137 R89, R94, R95, R97, R101-R117, R120-R122, R125-R136 J1, J2, J6-J8, J16-J18, J20, J22 10 F 0.0 33,000 51 47 H 0.1 F
Banana Jack, Socket Capacitor, 0.1 F, 20%, 12 V dc, 0805
Banana Hole CAP 0805
2 2 2 6 2 6
0.47 F 100 pF
Capacitor, 0.47 F, 5%, 12 V dc, 1206 Capacitor, 100 pF, 10%, 12 V dc, 0805 Connector, 40-pin Header Male St. Inductor, 47 H @ 100 MHz, 20%, IND2 IC, Differential Receiver, SOIC-8 Capacitor, 10 F, 20%, 16 V dc, 1812POL Resistor, 0.0 , 0805 Resistor, 33,000 , 5%, 0.10 Watt, 0805 Resistor, 51 , 5%, 0.10 Watt, 0805
Vitramon/VJ1206U474MFXMB Johansen/500R15N101JV4 Samtec/TSW-120-08-G-D Fair-Rite/2743019447 Motorola/MC10EP16D
CAP 1206 CAP 0805 HD40M IND2 MC10EP16D
Kemet/T491C106M016A57280
POLCAP 1812
4
Panasonic/ERJ-6GEY0R00V Panasonic/ERJ-6GEYJ333V Panasonic/ERJ-6GEYJ510V
RES2 0805 RES2 0805 RES2 0805, RES 0805
2 8
36
100
Resistor, 100 , 5%, 0.10 Watt, 0805
Panasonic/ERJ-6GEYJ101V
RES2 0805, RES 0805
8
Connector, SMA Female St.
Johnson Components/142-0701-201 SMA
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AD10465
Figure 10a. Top Layer Copper
Figure 10b. Second Layer Copper
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AD10465
Figure 10c. Third Layer Copper
Figure 10d. Fourth Layer Copper
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AD10465
Figure 10e. Fifth Layer Copper
Figure 10f. Bottom Layer Copper
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AD10465
Figure 10g. Bottom Silkscreen
Figure 10h. Bottom Assembly
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AD10465
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Ceramic Leaded Chip Carrier (ES-68A)
0.240 (6.096) 0.060 (1.52)
10
1.180 (29.97) SQ 0.950 (24.13) SQ
9 61 60
PIN 1
0.800 (20.32)
TOP VIEW
(PINS DOWN)
26 27 43
44
0.050 (1.27)
0.018 (0.457)
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PRINTED IN U.S.A.
C02356-4.5-1/01 (rev. 0)

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